We develop Memory Models, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our Memory Models are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our Memory Models are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.
All our Memory Models come with advanced commands, configurations, and status reporting interface. They are simple to use and debug. We use a lot of automation for writing Memory Models, so time to develop any Memory Model is very efficient and faster. If you need any Memory Model which is not listed below, please do let us know. We can develop it very fast for you.
We have more than 100 customers using our Verification IPs. Most of the top semiconductor companies are our customers.
