JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor provides a smart way to verify the JTAG component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's JTAG (IEEE 1149.1/1149.6) Synthesizable Transactor is fully compliant with standard JTAG Specification and provides the following features.
- Features
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- Follows JTAG basic specification as defined in JTAG Specification 3
- Supports Jtag protocol standard IEEE 1149.1 and IEEE 1149.6
- Supports all the JTAG tap instructions
- Supports programmable clock frequency of operation
- Supports checks for following
- Check-points include Initialization rules
- State based rules,Active Command rules
- Read/Write to Instruction and data register Rules
- Supports instruction register and data register of size up to 64 bits
- Supports proficiency to extend with user defined instructions and registers
- Has ability to read BSDL file and
- Automatically generate testvectors to test all BSDL cell types
- Automatically generate SVA assertions properties
- Supports all types of timing and protocol violation detection
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- JTAG (IEEE 1149.1/1149.6) Synthesizable Env
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SmartDV's JTAG (IEEE 1149.1/1149.6) Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the JTAG (IEEE 1149.1/1149.6) testcases
- Examples showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
