ICCAD China
Guangzhou PWTC Expo, Guangzhou, China
Postponed due to Covid, new date TBA
https://www.cicmag.com/bbx/1226773-1226773.html
IP Industry Transformation
June 9, 2022
Semiconductor Engineering
The Challenges Of Incremental Verification
April 28, 2022
Semiconductor Engineering
Growth Spurred By Negatives
January 27, 2022
Semiconductor Engineering
Industry Transforming In Ways Previously Unimaginable
December 30, 2021
Semiconductor Engineering
Outlook for 2022: Executive Viewpoints
December 2021, Page 61
Semiconductor Digest - Bipul Talukdar, Director of Applications Engineering for North America, SmartDV
Rapid Validation of Post-Silicon Devices Using Verification IP
November 9, 2021
Bipul Talukdar, Director of Applications Engineering for North America, SmartDV
Design and Verification IP: Insights From a SmartDV Insider
September 9, 2021
SemiWiki
The Complicated Chip Design Verification Landscape
May 24, 2021
Bipul Talukdar, Director of Applications Engineering for North America, SmartDV
Standards, Open Source, and Tools
May 10, 2021
Semiconductor Engineering
New Methodologies Create New Opportunities
April 27, 2021
Semiconductor Engineering
Verification In The Open Source Era
March 25, 2021
Semiconductor Engineering
SmartDV Shines in 2020!
February 17, 2021
SemiWiki
SmartDV – Electronic Design Industry Predictions
January 13, 2021
EDACafe - Bipul Talukdar, Director of Applications Engineering for North America, SmartDV
SmartDV Expands Its Design IP Portfolio with an Acquisition
December 29, 2020
SemiWiki
The Future of Chip Design
November 11, 2020
Bipul Talukdar, Director of Applications Engineering for North America, SmartDV
Is Hardware-Assisted Verification Avoidable?
October 29, 2020
Semiconductor Engineering
RISC-V: Will There Be Other Open-Source Cores?
October 6, 2020
Semiconductor Engineering
Productivity Keeping Pace With Complexity
September 24, 2020
Semiconductor Engineering
RISC-V: What’s Missing And Who’s Competing
September 23, 2020
Semiconductor Engineering
RISC-V’s CPU Verification Challenge
September 3, 2020
Bipul Talukdar, Director of Applications Engineering for North America, SmartDV
Components For Open-Source Verification
September 2, 2020
Semiconductor Engineering
RISC-V Gaining Traction
July 30, 2020
Semiconductor Engineering
Video: Fireside Chat with Bipul Talukdar from SmartDV
July 29, 2020
Axiomize Formal Bytes
The Quiet Giant in Verification IP and More
April 21, 2020
SemiWiki
The Thriving Silicon IP Business
April 2, 2020
Bipul Talukdar, Director of Applications Engineering for North America, SmartDV
Why It’s So Hard To Create New Processors
March 26, 2020
Semiconductor Engineering
11 Myths About Verification IP
December 11, 2019
Bipul Talukdar, Director of Applications Engineering for North America, SmartDV
Verification IP: An Essential Component of Today's Verification Strategy
Apr 10, 2019
Deepak Kumar Tala, CEO & Managing Director, SmartDV
SmartDV Achieves ISO 9001:2015 Certification
October 19, 2022
SmartDV Charts Course Toward Chiplets, Joins Universal Chiplet Interconnect Express (UCIe)
June 16, 2022
SmartDV Expands Executive Team with McKenzie Ross as Vice President of Marketing
April 7, 2022
SmartDV More Than Doubles Sales From 2020 to 2021
March 16, 2022
SmartDV and NSITEXE Sign Agreement to Deploy NSITEXE’s RISC-V 32bit CPU Core throughout North America, China, India, Taiwan
January 26, 2022
SmartDV Joins Open RF Association
January 13, 2022
SmartDV Announces Reusable Plug-and-Play Validation Solution
to Test Prototype Silicon
October 14, 2021
SmartDV Provides Broad Portfolio of Memory Modeling, Design and Verification Solutions
September 14, 2021
SmartDV Leads Industry with Greatest Number of Design and Verification MIPI Protocol Standards Solutions for Mobile Applications
July 29, 2021
SmartDV Joins the Xilinx Partner Program
June 17, 2021
SmartDV Announces Support for ARINC Standards
with Design and Verification IP
June 3, 2021
SmartDV Unveils Automation Tool Suite for Use with
Its Extensive Verification IP Portfolio
May 4, 2021
SmartDV 2020 Revenue Increases by 51%
February 3, 2021
SmartDV Announces New Line of Design IP Controllers for High-Speed Communications
December 9, 2020
SmartDV Appoints Karthik Gopal as Asia General Manager
October 22, 2020
SmartDV to Exhibit at Virtual Samsung SAFE Forum 2020 with Portfolio of Design and Verification IP
October 20, 2020
SmartDV Unveils SmartConf Testbench Generator
October 6, 2020
SmartDV Delivers First-to-Market MIPI A-PHY v1.0 Verification IP
September 22, 2020
SmartDV, Aldec Partner to Link SmartDV’s Verification IP with
Aldec’s Riviera-PRO Simulator
July 20, 2020
SmartDV Broadens Support for Arm AMBA Protocol with Verification IP Solutions for AMBA CHI, CSX, LPI
July 7, 2020
SmartDV’s Design and Verification Solutions Portfolio Surpasses 600 Offerings
June 9, 2020
SmartDV Delivers New Design IP for Video, Imaging, Entertainment System Protocols
June 4, 2020
SmartDV Ships First Design and Verification IP for MIPI RFFE v3.0 Specification
May 12, 2020
SmartDV’s LPDDR5 IP Clocks 612 MHz in FPGA Functional Test, 1.6GHz at 28nm
May 6, 2020
SmartDV Expands Line of Memory Controller Design IP, Strengthening its Already Broad Portfolio of IP Products
April 30, 2020
SmartDV Offers New Design IP for DDR5 and LPDDR5
February 18, 2020
SmartDV Adds Support for MIPI I3C 1.1 Across Entire IP Portfolio
February 12, 2020
SmartDV Achieves Record Revenue in 2019
February 4, 2020
NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications
December 10, 2019
SmartDV’s TileLink, Verilator VIP on Full Display at RISC-V Summit
December 3, 2019
SmartDV’s Platform-Independent VIP Portfolio Ensures Seamless Coverage-Driven Verification Flow
November 21, 2019
SmartDV to Exhibit at SemIsrael Expo, ICCAD China 2019
November 6, 2019
SmartDV Heads to DVCon Europe to Showcase VIP Support for Verilator and TileLink, Demonstrate Smart ViPDebug Protocol Debugger
October 17, 2019
SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator
October 1, 2019
SmartDV Announces Availability of Ethernet TSN Design IP
September 17, 2019
SmartDV to Demonstrate TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India
September 10, 2019
SmartDV to Exhibit at OpenPower Summit August 19-20
August 23, 2019
SmartDV Adds DisplayPort 2.0 to its Portfolio of Verification IP
July 16, 2019
SmartDV to Feature Smart ViPDebug, Extensive Portfolio of Verification, Design, Assertion, Post-Silicon IP, Synthesizable Transactors at ES Design West
June 27, 2019
SmartDV Adds New Verification IP to Support OpenCAPI Standard
June 25, 2019
SmartDV to Demonstrate New Smart ViPDebug Protocol Debugger at DAC
May 29, 2019
SmartDV Unveils First Verification IP to Support Ethernet TSN
May 23, 2019
SmartDV Appoints HyperSilicon Exclusive Sales Representative in China
May 9, 2019
SmartDV Speeds Delivery of its New CXL Verification IP
May 23, 2019
SmartDV Heads to ChipEx2019 in Israel with
Extensive Design and Verification IP Portfolio
May 7, 2019
SmartDV’s DVCon China Exhibit to Showcase Extensive Verification IP Portfolio
Apr 10, 2019
SmartDV Unveils SimXL Portfolio of Synthesizable Transactors for Hardware Emulation, FPGA Prototyping Platforms
Feb 14, 2019
SmartDV Supports RISC-V Movement with TileLink Verification IP for RISC-V Based Systems
Feb 6, 2019
