I start this note with a thank you to you, our customer base. This past year has been difficult for almost everyone across the globe. Yet, the semiconductor industry responded admirably with new chip design starts that will enable new electronic products to solve networking communications and so many more technological challenges.
It's gratifying to know SmartDV is playing a small but significant role. Our Verification and Design IP solutions are in use today in a variety of market segments, from networking, automotive and serial bus to storage, video and memory. You can find our solutions in design and verification projects in North America, Japan, Europe and Asia. Multi-year agreements and 26 new customers in 2020 helped grow our business by more than 51% over 2019. In 2020, we saw an increased licensing demand of close to 70% for Verification IP and a 300% increase in demand for Design IP solutions.
I’m extremely proud of our R&D group that includes more than 250 experienced ASIC and SoC design and verification engineers. In a tumultuous and confusing year, this group continued adding high-quality standard protocol Design and Verification IP to our portfolio and offering outstanding customer service.
As I noted in our previous newsletter, we are pleased that engineers like you rely on SmartDV for your Design and Verification IP. You have our ongoing commitment to support you and to rapidly customize Design and Verification IP for your specific applications and requirements.
Please enjoy the newsletter and give us your feedback. Comments, suggestions and questions are welcome.
Deepak Kumar Tala
Over the past several years, SmartDV has been expanding our product line by creating and introducing more and more Design IP based on increased demand from our customer base. Last December, we announced the acquisition of an entire portfolio of proven Design IP products targeting the mobile and high-speed communications applications markets. The silicon-realized, minimal area controller Design IP for MIPI and USB interfaces are available in Verilog or VHDL and are compliant with MIPI, UFS and USB standards. The Design IP is pre-verified and delivered as a comprehensive solution complete with a verification suite, CDC, synthesis and logic equivalence checking constraints and waivers, as applicable. They are reusable at the SoC level and proven interoperable with partner PHY solutions.
With the recent addition, our IP portfolio is now well over 600 products and growing with a significant percentage of Design IP. Expanding the footprint in Design IP means you now have a partner that can work with you early in the design cycle and follow through the verification process supporting simulation, emulation and formal, and ultimately, post-silicon validation.
Another benefit of working with SmartDV is our proprietary in-house SmartCompiler. This technology enables us to customize or modify Design IP rapidly using the automation provided by the compiler. This gives you an edge in being able to differentiate solutions based on specific market requirements that may be outside of the supported protocol.
In addition to our Design IP protocol support for MIPI, UFS and USB, we also have coverage for DDR, Ethernet, serial bus, audio/video, automotive, bridge, DMA, Flash memory and high-speed interfaces. With simple configurations and custom access, our bus interface Design IP offerings are available as an SoC Bus APB, AHB, AXI, TileLink, Wishbone or generic bus interface.
Our process for verifying newly created Design IP ensures your success. We first validate it against our proven Verification IP and then we fully test the Design IP using an FPGA platform. The final proof is in the actual prototype silicon that our partners produce.
View our latest SmartDV product directory to see what’s new in our IP product line.
From Semiwiki: SmartDV Shines in 2020!
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