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MIPI ASPMI Slave IIP

MIPI ASPMI Slave IIP

MIPI ASPMI Slave interface provides full support for the two-wire MIPI ASPMI synchronous serial interface, compatible with SPMI specification. Through its SPMI compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI ASPMI Slave IIP is proven in FPGA environment.The host interface of the MIPI ASPMI can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

MIPI ASPMI Slave IIP is supported natively in Verilog and VHDL

Features
  • Compliant with 1.7 ASPMI Slave Specification
  • Full MIPI SPMI 2.0 Slave functionality
  • Supports following frames
    • Command Frame
    • Data/Address Frame
    • No Response Frame
  • Supports ACK/NACK as per 2.0 specs
  • Support for slave requests through Alert(A) / Slave Request(SR) bit
  • Support for Slave Request Hold.
  • Glitch suppression (optional).
  • Supports extended register read/writes
  • Supports wakeup command
  • Supports Authentication Command Sequence
  • Supports Device Descriptor Block command Sequences
  • Supports following Device Interrupts
    • Edge sensitive interrupts
    • Level sensitive interrupts
    • Group interrupts
    • SPS (System Power State) interrupts
    • DVC Group interrupts
    • LDO and DVC interrupts
    • Interrupt priority queuing
    • IRQH Enable register (Disabling of IRQ generation functionality based on NACK Retry limit)
    • Generation of Group event on any internal SPMI error logged in an ERROR CTRL register
  • Supports virtual wires on SPMI (Supports both scheme 1 and scheme 2)
  • Supports Short Addressing Modes
  • Supports Control on Register0 write and power mode command (Sleep/Wakeup/Shutdown/Reset) reception
  • Supports Slave To Slave (STS) Transmit and Receive Command filtering
  • Supports SGPIO functionality
  • Ability to generate an empty arbitration request
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices
  • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
Benefits
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables

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    SmartDV's MIPI ASPMI Slave IP contains following.

  • The MIPI ASPMI Slave interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.
  • ISO26262 Safety Manual (SAM) Document
  • ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document

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