MIPI MPHY Synthesizable Transactor provides a smart way to verify the MIPI MPHY component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's MIPI MPHY Synthesizable Transactor is fully compliant with standard 3.0, 4.0 MIPI MPHY Specifications and provides the following features.
- Features
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- Supports 3.0, 4.0 MIPI MPHY Specification
- Support Type-1 and Type-II operations
- Supports both serial and protocol layer interface
- Supports all PWM 0-7 gear of operation
- Supports all HS 1, 2, 3, 4 gear of operation
- Supports Serial recovers clock from input serial data stream
- Supports clock recovery
- Supports disabling of NRZ and PWM for easy serial debugging
- Support all LCC commands
- Support fine grain control of each timing parameter
- Support timing checks to validate each timing period
- Support programmable sync pattern and length
- Support following 8b/10b error insertion and detection:
- Invalid K character injection
- Injection of disparity errors
- Wrong K character injection
- Corruption of Marker characters
- Supports periodic Filler (NOP) insertion
- Supports periodic Marker 1 insertion
- Supports periodic fixed pattern sending to verify MPHY support for PCI Express, Unipro
- Supports inband reset signaling and detection
- Supports Test Pattern generation and checking (CJTPAT and CRPAT)
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- MIPI MPHY Synthesizable Transactor Env
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SmartDV's MIPI MPHY Synthesizable Transactor env contains following:
- Synthesizable transactors
- Complete regression suite containing all the MIPI MPHY testcases
- Examples showing how to connect various components, and usage of Synthesizable Memory model
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
