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Serial NOR Flash Synthesizable Transactor

Serial NOR Flash Synthesizable Transactor

Serial NOR Flash Synthesizable Transactor provides a smart way to verify the Serial NOR Flash component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's Serial NOR Flash Synthesizable Transactor is fully compliant with standard Serial NOR Flash Specification and provides the following features.

Features
  • Supports 100% of Serial NOR Flash protocol standard
  • Supports all the Serial NOR Flash commands as per the specs
  • Supports single and double transfer rate (STR/DTR)
  • Supports following protocols in both STR and DTR:
    • Extended I/O protocol
    • Dual I/O protocol
    • Quad I/O protocol
  • Supports execute-in-place (XIP)
  • Supports volatile and nonvolatile configuration settings
  • Supports software reset
  • Supports 3-byte and 4-byte addressing modes
  • Supports 64-byte OTP area outside main memory
    • Readable and user-lockable
    • Permanent lock with program OTP commands
  • Supports program/erase suspend operation
  • Supports the following erase capability
    • Die erase
    • Sector erase 64KB uniform granularity
    • Subsector erase 4KB, 32KB granularity
  • Supports security and write protection
    • Nonvolatile configuration locking
    • Password protection
    • Hardware write protection
    • CRC detects accidental changes in raw data
  • Supports all types of timing and protocol violation detection
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
Serial NOR Flash Synthesizable Transactor Env

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    SmartDV's Serial NOR Flash Synthesizable Transactor env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the Serial NOR Flash testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

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