LPDDR4 DFI Synthesizable Transactor provides a smart way to verify the LPDDR4 DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's LPDDR4 DFI Synthesizable Transactor is fully compliant with standard DFI Specification and provides the following features.
- Features
-
- Compliant with DFI version 4.0 or 5.0 Specifications.
- Supports LPDDR4 devices compliant with JEDEC LPDDR4 SDRAM Standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4X and LPDDR4Y (Proposed).
- Supports for Read data-eye training
- Supports for Read gate training
- Supports for Write leveling
- Supports for Write date-eye training
- Supports for CA training
- Supports for Read data bus inversion
- Supports for Write data bus inversion
- Supports for Combined and multi-configuration channel support
- Supports for DFI disconnect during training
- Supports for Write data mask and data strobe features..
- Supports for ZQ/DQ Calibration commands.
- Supports for Byte mode.
- Supports for Single-ended mode.
- Supports for Power Down features.
- Supports for Self refresh.
- Supports for Programmable READ/WRITE Latency timings.
- Supports for both 16 and 32 Programmable burst lengths.
- Supports for Burst sequence.
- Supports DRAM Clock disabling feature.
- Supports Error signaling.
- Supports Independent Operation & Multi-Configuration Support for DFI LPDDR4.
- Supports all types of timing and protocol violations detection for timing parameters.
- Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI version 4.0 or 5.0 Specifications.
- Benefits
-
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- LPDDR4 DFI Synthesizable Transactor Env
-
SmartDV's LPDDR4 DFI Synthesizable Transactor env contains following:
- Synthesiable transactors
- Complete regression suite containing all the LPDDR4 DFI testcases
- Example's showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation also contains User's Guide and Release notes
