BISS Verification IP provides an smart way to verify the BISS component of a SOC or a ASIC. The SmartDV's BISS Verification IP is fully compliant with standard BISS Specification and provides the following features.
BISS Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
BISS Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Fully compatible with Standard BISS Specification.
- Transmit and receive commands allow the user to transmit and receive BISS data.
- Configurable Baud rate control.
- Fully configurable serial interface.
- Configurable receive FIFO depth.
- Supports constraints Randomization.
- Callbacks in Master, Device and monitor for user processing of data.
- Supports for standardized data format.
- Supports BISS standard rotary encoder.
- Supports point-to-point and bus configuration.
- Supports broadcast and addressed command frame.
- Supports MA clock frequency from 80 KHZ.
- Notifies the test bench of significant events such as transactions, warnings, and protocol violations.
- BISS Verification IP comes with complete test suite to verify each and every feature of BISS specification.
- Status counters for various events in bus.
- Functional coverage for complete features.
- Benefits
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- Faster testbench development and more complete verification of BISS designs.
- Easy to use command interface simplifies testbench control and configuration of Master and Device.
- Simplifies results analysis.
- Runs in every major simulation environment.
- BISS Verification Env
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SmartDV's BISS Verification env contains following.
- Complete regression suite containing all the BISS testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
