LPDDR4 DFI Verification IP provides an smart way to verify the LPDDR4 DFI component of a SOC or a ASIC. The SmartDV's LPDDR4 DFI Verification IP is fully compliant with standard DFI Specification and provides the following features.
LPDDR4 DFI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
LPDDR4 DFI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
-
- Compliant with DFI version 4.0 or 5.0 Specifications.
- Supports LPDDR4 devices compliant with JEDEC LPDDR4 SDRAM Standard JESD209-4, JESD209-4A, JESD209-4B, JESD209-4C (Proposed), JESD209-4X and LPDDR4Y (Proposed).
- Supports for Read data-eye training
- Supports for Read gate training
- Supports for Write leveling
- Supports for Write date-eye training
- Supports for CA training
- Supports for Read data bus inversion
- Supports for Write data bus inversion
- Supports for Combined and multi-configuration channel support
- Supports for DFI disconnect during training
- Supports for Write data mask and data strobe features..
- Supports for ZQ/DQ Calibration commands.
- Supports for Byte mode.
- Supports for Single-ended mode.
- Supports for Power Down features.
- Supports for Self refresh.
- Supports for Programmable READ/WRITE Latency timings.
- Supports for both 16 and 32 Programmable burst lengths.
- Supports for Burst sequence.
- Supports for input clock stop and frequency change.
- Supports DRAM Clock disabling feature.
- Supports Error signaling.
- Supports Independent Operation & Multi-Configuration Support for LPDDR4.
- Supports all types of timing and protocol violations detection for timing parameters.
- Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI version 4.0 or 5.0 Specifications.
- Bus-accurate timing for min, max and typical values.
- Notifies the test bench of significant events such as transactions, warnings.
- Built in functional coverage analysis.
- Supports callbacks, so that user can access the data observed by monitor.
- Benefits
-
- Faster test bench development and more complete verification of LPDDR4 DFI designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- LPDDR4 DFI Verification Env
-
SmartDV's LPDDR4 DFI Verification env contains following.
- Complete regression suite containing all the LPDDR4 DFI testcases.
- Complete UVM/OVM sequence library for LPDDR4 DFI controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation also contains User's Guide and Release notes.
