• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IPs
      • MIPI Verification IPs
      • Networking and SOC Verification IPs
      • Automotive And Serial Bus Verification IPs
      • Storage And Video Verification IPs
    • Memory Models
      • DDR SDRAM Memory Models
      • DFI Verification IPs
      • DIMM Memory Models
      • Flash Memory Models
      • Graphics Memory Models
      • High Bandwidth Memory Models
      • Low Power Memory Models
      • Misc Memory Models
      • Non volatile Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • Non volatile Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
      • DFI Synthesizable Transactors
    • Formal Verification IPs (Assertion IP)
      • Networking and SOC Assertion IPs
      • DDR SDRAM Memory Assertion IPs
      • Low Power Memory Assertion IPs
      • Graphics Memory Assertion IPs
      • High Bandwidth Memory Assertion IPs
      • SDRAM Memory Assertion IPs
      • DFI Assertion IPs
      • Serial Assertion IPs
    • Post Silicon Validation IPs
      • MIPI Post Silicon Validation IPs
    • Design IPs
      • DDR Controller Design IPs
      • Ethernet Design IPs
      • Serial Bus Design IPs
      • Audio Video Design IPs
      • MIPI Design IPs
      • Automotive Design IPs
      • Bridge Design IPs
      • DMA Controller Design IPs
      • Flash Controller Design IPs
      • High Speed Design IPs
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

MIPI I3C Synthesizable Transactor

MIPI I3C Synthesizable Transactor

MIPI I3C Synthesizable Transactor provides a smart way to verify the MIPI I3C component of a SOC or a ASIC in Emulator or FPGA platform. MIPI I3C Synthesizable Transactor provides an smart way to verify the MIPI I3C bi-directional two-wire bus. The SmartDV's MIPI I3C Synthesizable Transactor is fully compliant with Specification for I3C version 1.1 and provides the following features.

Features
  • Compliant with MIPI I3C version 1.1 specification
  • Supports full MIPI I3C Master and Slave functionality
  • Two wire serial interface up to 12.5 MHz using Push-Pull with the following Data rates supported
    • Standard speed
  • Supports all topologies
    • Single master – Single slave
    • Single master – Multi slave
    • Multi master – Single slave
    • Multi master – Multi slave
  • Dynamic Addressing while supporting Static Addressing for legacy I2C devices.
  • Supports I3C address arbitration.
  • Supports Single Data Rate (SDR) messaging.
    • Direct CCC
    • Broadcast CCC
  • Supports High Data Rate (HDR) messaging
    • HDR-Dual Data Rate Mode (HDR-DDR)
    • HDR-Ternary symbol for Pure bus (HDR-TSP)
    • HDR-Ternary symbol Legacy inclusive bus (HDR-TSL)
  • In-Band Interrupt support and Hot-Join support
  • Legacy I2C Device co-existence on the same Bus instance
  • Supports error detection and recovery
  • Supports injection of various errors by master
    • Broadcast address/ I3C address error
    • SDR write data parity error
    • Dynamic address parity error
    • Illegal CCC error
    • HDR command parity and preamble error
    • HDR write data parity and preamble error
    • HDR CRC and frame error
  • Supports injection of various errors by slave
    • Broadcast address/ I3C address nack error
    • Illegal CCC error
    • I2C write data nack error
    • SDR read data parity error
    • HDR read data preamble and parity error
    • HDR read CRC error
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
MIPI I3C Synthesizable Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's MIPI I3C Synthesizable env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the MIPI I3C testcases
  • Examples showing how to connect various components, and usage of Synthesiable VIP
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

About SmartDV
Partners
Careers
Products
Customers
News & Events

Verification IP
Memory Models
SimXL - Emulation Models
Formal Verification IP (Assertion IP)
Post-Silicon Validation IP
Design IP

info@smart-dv.com

Contact Us
Support

Copyright © SmartDV Technologies India Private Limited All rights reserved.