GDDR5X Assertion IP provides an efficient and smart way to verify the GDDR5X designs quickly without a testbench. The SmartDV's GDDR5X Assertion IP is fully compliant with standard GDDR5X Specification.
GDDR5X Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
GDDR5X Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Supports GDDR5X memory devices from all leading vendors.
- Supports 100% of GDDR5X protocol standard JESD232 and JESD232A.
- Supports all the GDDR5X commands as per the specs.
- Quickly validates the implementation of the GDDR5X standard JESD232 and JESD232A.
- Supports for all types of timing and protocol violation detection.
- Supports up to 16GB device density.
- Supports the following device modes.
- X16
- X32
- Supports for All Mode register programming.
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- All timing violations.
- Supports for Single ended interface for command, address and data.
- Supports for QDR and DDR operating mode.
- Supports for Programmable read latency and write latency.
- Supports for Write data mask function via address bus.
- Supports for Data bus inversion (DBI) & address bus inversion (ABI).
- Supports for Address training.
- Supports for RDQS Mode.
- Supports for Bank group features.
- Supports for DQ preamble.
- Supports for cyclic redundancy check (CRC-8).
- Supports for Programmable CRC read latency and write latency.
- Supports for Low Power modes.
- Supports for Auto Precharge option for each burst access.
- Supports Mirror function with MF pin.
- Supports IEEE 1149.1 compliant boundary scan.
- Constantly monitors GDDR5X behavior during simulation.
- Protocol checker fully compliant with GDDR5X Specification JESD232 and
- JESD232A.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV GDDR5X VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure GDDR5X Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- GDDR5X Assertion Env
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SmartDV's GDDR5X Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
