HBM3 Memory Model provides an smart way to verify the HBM3 component of a SOC or a ASIC. The SmartDV's HBM3 memory model is fully compliant with standard HBM3 Specification and provides the following features. Better than Denali Memory Models.
HBM3 Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
HBM3 Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports HBM3 memory devices from all leading vendors.
- Supports 100% of HBM3 protocol draft JEDEC specification version 1.1.
- Supports all the HBM3 commands as per the specs.
- Supports programmable clock frequency of operation.
- Support all types of timing and protocol violation detection.
- Supports burst length 8.
- Supports programmable READ/WRITE Latency timings.
- Supports Bank grouping.
- Supports 16,32 or 48 banks per channel based on device density and channel.
- Supports 2KB page size per channel.
- Supports up to 16 channels per stack.
- Supports semi-independent row and column command interfaces.
- Supports WDQS-to-CK training.
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Commands rules etc.
- All timing violations.
- Supports callbacks for user to get command data on bus.
- Supports all Mode registers programming.
- Supports DBIac write and read.
- Supports Pseudo Channel Mode Operation (32 DQ width for Pseudo Channel Mode).
- Supports 2 Pseudo channels per channel.
- Supports Self-Refresh Modes.
- Supports IEEE standard 1500.
- Supports channel density of 2 GB to 32 GB.
- Supports 64 DQ width + Optional ECC pin support/channel.
- Supports write data mask and data strobe features.
- Supports for power down features.
- Supports for input clock stop and frequency change.
- Bus-accurate timing for min, max and typical values.
- Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Constantly monitors HBM3 behavior during simulation.
- Protocol checker fully compliant with HBM3 JEDEC draft Specification version 1.1.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations.
- Built in functional coverage analysis.
- Supports callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster testbench development and more complete verification of HBM3 designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- HBM3 Verification Env
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SmartDV's HBM3 Verification env contains following.
- Complete regression suite containing all the HBM3 testcases.
- Complete UVM/OVM sequence library for HBM3 controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
