MIPI I3C Slave To AXI Bridge interface provides full support for the two-wire MIPI I3C synchronous serial interface, compatible with MIPI I3C version 2.0 standard.Through its MIPI I3C compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI I3C Slave To AXI Bridge IIP is proven in FPGA environment.The host interface of the MIPI I3C can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
MIPI I3C Slave To AXI Bridge IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with the I3C version 2.0 specification.
- Full MIPI I3C Slave functionality.
- Convert MIPI I3C Transactions into AXI write or read instructions
- Allows external devices to access the internal AXI Bus
- Useful for updating device software from and external device
- Useful for reading internal memory mapped registers and memory
- Supports Mailbox Read/Write functionality
- Supports AXI Master Read/ Write capability
- Supports AXI Slave
- Supports monitoring of erroneous AXI transfers and reports error to the system
- Supports flexible transfer format to work with slower interfaces
- Supports address width of 8,16,24 and 32 bits
- Two wire serial interface up to 12.5 MHz using Push-Pull with the following Data rates supported.
- Supports the following topologies
- Single Master-Multi Slave
- Single Master-Single Slave
- I2C legacy device support
- Supports Single Data Rate (SDR) messaging.
- SDR with CCC Directed addressing
- SDR with CCC Broadcasted addressing
- Supports High Data Rate (HDR) messaging
- HDR-Dual Data Rate Mode (HDR-DDR)
- In-Band Interrupt support
- Hot-Join support
- Dynamic Address Assignment support (DAA).
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to microprocessor/microcontroller devices.
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's MIPI I3C Slave To AXI Bridge IP contains following
- The MIPI I3C SLAVE To AXI Bridge interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
