• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IPs
      • MIPI Verification IPs
      • Networking and SOC Verification IPs
      • Automotive And Serial Bus Verification IPs
      • Storage And Video Verification IPs
    • Memory Models
      • DDR SDRAM Memory Models
      • DFI Verification IPs
      • DIMM Memory Models
      • Flash Memory Models
      • Graphics Memory Models
      • High Bandwidth Memory Models
      • Low Power Memory Models
      • Misc Memory Models
      • Non volatile Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • Non volatile Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
      • DFI Synthesizable Transactors
    • Formal Verification IPs (Assertion IP)
      • Networking and SOC Assertion IPs
      • DDR SDRAM Memory Assertion IPs
      • Low Power Memory Assertion IPs
      • Graphics Memory Assertion IPs
      • High Bandwidth Memory Assertion IPs
      • SDRAM Memory Assertion IPs
      • DFI Assertion IPs
      • Serial Assertion IPs
    • Post Silicon Validation IPs
      • MIPI Post Silicon Validation IPs
    • Design IPs
      • DDR Controller Design IPs
      • Ethernet Design IPs
      • Serial Bus Design IPs
      • Audio Video Design IPs
      • MIPI Design IPs
      • Automotive Design IPs
      • Bridge Design IPs
      • DMA Controller Design IPs
      • Flash Controller Design IPs
      • High Speed Design IPs
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

DDR4 3DS DIMM Memory Model

DDR4 3DS DIMM Memory Model

DDR4 3DS DIMM Memory Model provides an smart way to verify the DDR4 3DS DIMM component of a SOC or a ASIC. The SmartDV's DDR4 3DS DIMM memory model is fully compliant with standard DDR4 3DS DIMM Specification and provides the following features. Better than Denali Memory Models.

DDR4 3DS DIMM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR4 3DS DIMM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Supports DDR4 3DS DIMM memory devices from all leading vendors.
  • Supports 100% of DDR4 3DS DIMM protocol standard JESD79-4-1,JESD79-4-1A.
  • Supports all the DDR4 3DS RDIMM and LRDIMM types.
  • Supports up to 16GB device density.
  • Supports ECC Error detection and Error correction
  • Supports X4 and X8 devices.
  • Supports all speed grades as per specification.
  • Quickly validates the implementation of the DDR4 3DS DIMM standard JESD79-4-1, JESD79-4-1A.
  • Supports 2 Package ranks x4 logic ranks.
  • Supports On-the-fly protocol and data checking.
  • Supports Programmable Write latency and Read latency.
  • Supports Programmable burst lengths: 4, 8.
  • Supports Programmable Preamble.
  • Supports Read preamble training.
  • Supports the following burst types.
    • Sequential
    • Interleave
  • Supports burst order.
  • Checks for following
    • Check-points include power up, initialization and power off rules
    • State based rules, Active Command rules
    • Read/Write Command rules etc.,
    • All timing violations
  • Supports all mode register programming.
  • Supports Data Mask and Data Bus Inversion (DBI).
  • Supports write leveling for calibrations and ZQ Calibration commands.
  • Supports Fine Granularity Refresh Mode.
  • Supports Multipurpose Register.
  • Supports DQ Vref training.
  • Supports CRC for Write Operations.
  • Supports DLL features.
  • Supports Command Address Parity features.
  • Supports Post Package Repair (PPR).
  • Supports Control Gear down mode and CAL Mode Operation.
  • Supports Per DRAM Addressability.
  • Supports Connectivity Test (CT) mode.
  • Supports both Synchronous and Asynchronous On-Die Termination modes.
  • Supports Power Down features and Maximum Power Saving mode.
  • Supports input clock stop and frequency change.
  • Protocol checker fully compliant with DDR4 3DS DIMM Specification JESD79-4-1, JESD79-4-1A.
  • Constantly monitors DDR4 3DS DIMM behavior during simulation.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.
Benefits
  • Faster testbench development and more complete verification of DDR4 3DS DIMM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
DDR4 3DS DIMM Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's DDR4 3DS DIMM Verification env contains following.

  • Complete regression suite containing all the DDR4 3DS DIMM testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

About SmartDV
Partners
Careers
Products
Customers
News & Events

Verification IP
Memory Models
SimXL - Emulation Models
Formal Verification IP (Assertion IP)
Post-Silicon Validation IP
Design IP

info@smart-dv.com

Contact Us
Support

Copyright © SmartDV Technologies India Private Limited All rights reserved.