SAE J2716 Sensor interface provides full support for the SENT SAE J2716 synchronous serial interface, compatible with SENT specification SAE J2716 APR2016. Through its SAE J2716 compatibility, it provides a simple interface to a wide range of low-cost devices. SAE J2716 Sensor IIP is proven in FPGA environment.The host interface of the SAE J2716 can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
SAE J2716 Sensor IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with SENT specification SAE J2716 APRIL2016
- Supports optional SPC protocol to enhance the SENT protocol
- Supports all types of frames
- Short Serial Message Format
- Enhanced Serial Message Format
- Enhanced Serial Message Format supports two different configurations
- 12-bit data and 8-bit message ID
- 16-bit data and 4-bit message ID
- Supports programmable clock frequency of operation
- Supports programmable number of data nibbles
- Supports programmable length for calibration pulse
- Supports programmable length for minimum nibble pulse period
- Minimum length - 12 clock ticks
- Maximum length - 27 clock ticks
- Supports pause pulse properties
- Minimum length - 12 clock ticks
- Maximum length - 768 clock ticks
- Supports both 4-bit CRC and 6-bit CRC
- Supports interrupt handling when transmission is done
- Supports all types of error injection
- Calibration low minimum and maximum error
- Calibration high minimum and maximum error
- Nibble minimum and maximum value error
- Frame CRC and Status nibble CRC error
- Minimum and maximum pause length error
- Short serial start bit error
- Unique pattern error
- Supports Sent data frame formats
- Two 12-bit fast channels (6 data nibbles)
- One 12-bit fast channel (3 data nibbles)
- High-speed with one 12-bit fast channel (4 data nibbles, where only values 0-7 are used)
- Secure sensor with 12-bit fast channel 1 and secure sensor information on fast channel 2 (6 data nibbles)
- Single sensor with 12-bit fast channel 1 and zero value on fast channel 2 (6 data nibbles)
- Two fast channels with 14-bit fast channel 1 and 10-bit fast channel 2 (6 data nibbles)
- Two fast channels with 16-bit fast channel 1 and 8-bit fast channel 2 (6 data nibbles)
- Fully Synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to sensors.
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's SAE J2716 Sensor IP contains following
- The SAE J2716 Sensor interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
