SATA HOST CONTROLLER core is compliant with SATA version 3.5 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. SATA HOST CONTROLLER IIP is proven in FPGA environment. The host interface of the SATA can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
SATA HOST CONTROLLER IIP is supported natively in Verilog and VHDL
- Features
-
- Supports SATA specs 2.5/2.6/3.0/3.1/3.2/3.3/3.4/3.5.
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller
- devices
- Supports 1.5 Gbit/s, 3.0 Gbit/s and 6.0 Gbit/s data transfer rates
- Supports DMA and PIO commands
- Hardware support for
- 48-bit address set
- Detection of OOB, COMWAKE, K28.5, etc.
- 8b/10b coding and decoding
- CRC generation and checking
- Auto insertion of HOLD primitives
- Native Command Queuing (NCQ)
- Port Multiplier, Port Selector
- First Party DMA (FPDMA)
- CONT primitive support for primitive suppression to reduce EMI
- Implements the shadow register block and the serial ATA status and control
- registers
- Complete Link Layer state machine.
- Selectable data scrambling option.
- Supports link layer power modes.
- Benefits
-
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
-
SmartDV's SATA Host Controller IP contains following
- The SATA Host Controller interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
