• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IPs
      • MIPI Verification IPs
      • Networking and SOC Verification IPs
      • Automotive And Serial Bus Verification IPs
      • Storage And Video Verification IPs
    • Memory Models
      • DDR SDRAM Memory Models
      • DFI Verification IPs
      • DIMM Memory Models
      • Flash Memory Models
      • Graphics Memory Models
      • High Bandwidth Memory Models
      • Low Power Memory Models
      • Misc Memory Models
      • Non volatile Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • Non volatile Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
      • DFI Synthesizable Transactors
    • Formal Verification IPs (Assertion IP)
      • Networking and SOC Assertion IPs
      • DDR SDRAM Memory Assertion IPs
      • Low Power Memory Assertion IPs
      • Graphics Memory Assertion IPs
      • High Bandwidth Memory Assertion IPs
      • SDRAM Memory Assertion IPs
      • DFI Assertion IPs
      • Serial Assertion IPs
    • Post Silicon Validation IPs
      • MIPI Post Silicon Validation IPs
    • Design IPs
      • DDR Controller Design IPs
      • Ethernet Design IPs
      • Serial Bus Design IPs
      • Audio Video Design IPs
      • MIPI Design IPs
      • Automotive Design IPs
      • Bridge Design IPs
      • DMA Controller Design IPs
      • Flash Controller Design IPs
      • High Speed Design IPs
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

LPDDR Memory Model

LPDDR Memory Model

LPDDR Memory Model provides an smart way to verify the LPDDR component of a SOC or a ASIC. The SmartDV's LPDDR memory model is fully compliant with standard LPDDR Specification and provides the following features. Better than Denali Memory Models.

LPDDR Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

LPDDR Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Supports LPDDR memory devices from all leading vendors.
  • Supports 100% of LPDDR protocol standard JESD209B and JESD209A-1.
  • Supports all the LPDDR commands as per the specs.
  • Supports up to 2GB device density
  • Supports the following devices.
    • X16
    • X32
  • Supports all speed grades as per specification.
  • Quickly validates the implementation of the LPDDR standard JESD209B and JESD209A-1.
  • Supports Programmable CAS latency.
  • Supports Programmable burst lengths: 2, 4, 8 and 16.
  • Checks for following
    • Check-points include power up, initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Supports for All Mode registers/Control programming.
  • Supports for Extended Mode register programming.
  • Supports for the following Burst Types,
    • Sequential
    • Interleave
  • Supports for Burst order.
  • Supports for Write data Mask.
  • Supports for Power Down features.
  • Supports for Deep Power Down features.
  • Supports for Auto Precharge option for each burst access
  • Supports for Auto Refresh and Self Refresh Modes
  • Supports for input clock stop and frequency change.
  • Supports for full-timing as well as behavioral versions in one model.
  • Supports for all timing delay ranges in one model: min, typical and max.
  • Optional Partial Array Self Refresh and Temperature Compensated Self Refresh
  • Constantly monitors LPDDR behavior during simulation.
  • Protocol checker fully compliant with LPDDR Specification JESD209B and JESD209A-1.
  • Model detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.
Benefits
  • Faster testbench development and more complete verification of LPDDR designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
LPDDR Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's LPDDR Verification env contains following.

  • Complete regression suite containing all the LPDDR testcases.
  • Complete UVM/OVM sequence library for LPDDR controller.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

About SmartDV
Partners
Careers
Products
Customers
News & Events

Verification IP
Memory Models
SimXL - Emulation Models
Formal Verification IP (Assertion IP)
Post-Silicon Validation IP
Design IP

info@smart-dv.com

Contact Us
Support

Copyright © SmartDV Technologies India Private Limited All rights reserved.