SMBUS Assertion IP provides an efficient and smart way to verify the SMBUS designs quickly without a testbench. The SmartDV's SMBUS Assertion IP is fully compliant with standard SMBUS Specification.
SMBUS Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SMBUS Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Supports SMBus specification version 3.0.
- Supports all the SMBus commands as per the specs.
- Supports programmable clock frequency of operation.
- Support ARP command generation and response.
- Support Timeout detection and generation.
- Bus-accurate timing.
- Packet Error Checking support.
- Wrong ARP Address
- Unsupported command codes
- Illegal command lengths
- Support for multiple instantiations to create complex verification environment.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV SMBUS VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure SMBUS Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- SMBUS Assertion Env
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SmartDV's SMBUS Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
