AHB Decoder IP core is compliant with AMBA AHB Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices.AHB Decoder IIP is proven in FPGA environment.
AHB Decoder IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with AMBA AHB specification
- Supports configurable number of AHB Master
- Supports configurable number of AHB Slave
- types, burst transfers and response types
- Support for all the transfer sizes
- Supports configurable Endianness of the Data bus
- Supports feature of decoder to decode address from master and to map to the respective slave on the AHB Channel
- Supports multiplexor to select the read data slaves and to route to respective AHB Master on the bus
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's AHB Decoder Bridge IP contains following
- The AHB Decoder is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
