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GDDR7 Synthesizable Transactor

GDDR7 Synthesizable Transactor

GDDR7 Synthesizable Transactor provides a smart way to verify the GDDR7 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's GDDR7 Synthesizable Transactor is fully compliant with standard GDDR7 Specification and provides the following features.

Features
  • Supports GDDR7 memory devices from all leading vendors.
  • Supports 100% of GDDR7 protocol draft JEDEC specification.
  • Supports all the GDDR7 commands as per the specs.
  • Supports 4 separate independent channels with point-to-point interface for data, address and command.
  • Supports command parity
  • Supports Double Data Rate (DDR).
  • Supports Pseudo channel mode operation.
  • Supports 16 - 64 Gbit densities
  • Supports X8 mode.
  • Supports RDQS mode.
  • Supports DQ preamble.
  • Supports Bank group features.
  • Supports Programmable Read/Write latency.
  • Supports Bank grouping and 16 internal banks per channel.
  • Supports Data bus inversion (DBI) & Command Address bus inversion (CABI).
  • Supports Read/Write data transmission integrity secured by cyclic redundancy check.
  • Supports ECC.
  • Supports Input/output PLL/DLL on/off mode.
  • Supports Read/Write EDC on/off mode.
  • Supports Programmable EDC hold pattern for CDR.
  • Supports Programmable CRC Read/Write latency.
  • Supports Low Power modes.
  • Supports Auto refresh & self-refresh modes.
  • Supports On-die termination operation.
  • Supports Command Address, WCK2CK, Read, and Write Training mode’s.
  • Supports IEEE.1149.1 boundary scan operation.
  • Checks for following
    • Check-points include power on, Initialization and power off rules,
    • State based rules, Active Command rules,
    • Read/Write Command rules etc.
    • All timing violations.
  • Supports callbacks for user to get command data on bus.
  • Supports all mode registers programming.
  • Supports for power down features.
  • Quickly validates the implementation of the GDDR7 protocol JEDEC draft specification.
  • Bus-accurate timing for min, max and typical values.
  • Constantly monitors GDDR7 behavior during simulation.
  • Protocol checker fully compliant with GDDR7 JEDEC draft specification.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.
  • Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
GDDR7 Synthesizable Transactor Env

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    SmartDV's GDDR7 Synthesizable Transactor env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the GDDR7 testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

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