FEC RS (544,514) core is compliant with standard CPRI 7.0 Specification, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. FEC RS (544,514) IIP is proven in FPGA environment.
FEC RS (544,514) IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with CPRI Specification V7.0, IEEE Standard 802.3.2018 Ethernet specification and JESD204D Specification.
- Supports full FEC functionality.
- Supports Reed Solomon (544,514) FEC, 10-bit symbols.
- Supports different input and output data widths of multiples of 10-bits.
- Supports the parity generation of 300 bits.
- Supports the bit locker mechanism.
- Supports the Syndrome calculation.
- Supports the Berlekamp's algorithm.
- Supports the Chien search for error position.
- Supports the Error correction of 150 bits.
- Supports up to the 15 symbols of error correction.
- Supports the pipelined mechanism for the error correction.
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's FEC RS (544,514) IP contains following
- The FEC RS (544,514) interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- Documentation contains User's Guide and Release notes.
