MIPI_DEBUG_UART Verification IP provides an smart way to verify the MIPI_DEBUG_UART component of a SOC or a ASIC. The SmartDV's MIPI_DEBUG_UART Verification IP is fully compliant with MIPI_DEBUG_UART DDI0183G_uart_pl011_r1p5_trm Specification and provides the following features.
MIPI_DEBUG_UART Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
MIPI_DEBUG_UART Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- APB common support
- Supports different transfer types including IDLE, WRITE and READ.
- Supports unaligned address accesses.
- Slave memory map support.
- Supports Unmapped address accesses.
- Programmable number of idle cycles
- Ability to inject errors during data transfer.
- Supports FIFO memory.
- Transmit and receive commands allow the user to transmit and receive data.
- Supports character width from 1 bit to 32 bits.
- Configurable receive FIFO depth.
- Supports constraints Randomization.
- Callbacks in transmitter, receiver and monitor for user processing of data.
- On-the-fly protocol and data checking.
- Ability to transmit strings to help verification of SOC.
- Notifies the testbench of significant events such as transactions, warnings, and protocol violations.
- UART Adaptor Verification IP comes with complete testsuite to verify each and every feature of UART Adaptor specification.
- Benefits
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- Faster testbench development and more complete verification of designs.
- Easy to use command interface simplifies test bench control and configuration of master and slave.
- Simplifies results analysis.
- Integrates easily into Open Vera, System Verilog, and Verilog.
- Runs in every major simulation environment.
- MIPI_DEBUG_UART Verification Env
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SmartDV's MIPI_DEBUG_UART Verification env contains following.
- Complete regression suite containing all the MIPI_DEBUG_UART testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
