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JESD204 Synthesizable Transactor

JESD204 Synthesizable Transactor

The JESD204 Synthesizable Transactor is compliant with JESD204 revision A/B/C specifications and verifies JESD204 interfaces. JESD204 is build on top of it to make it robust. JESD204 Synthesizable Transactor provides a smart way to verify the JESD204 component of a SOC or a ASIC in Emulator or FPGA platform.JESD204 Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

Features
  • Follows JESD204 specification JESD204A, JESD204B and JESD204C
  • Supports Transmitter and Receiver Mode
  • Supports up to 32 lanes
  • Supports 32bit data width per converter
  • Supports up to 32 converters per transmitter & receiver BFM
  • Scrambler can be enabled or disabled
  • Supports 8b/10b link layer functions
  • Supports 64b/66b link layer functions based on IEE802.3 Clause 49 and JESD204C
  • Supports 64b/80b link layer functions with fill bit encoding based on IEEE802.3 clause 49 and JESD204C
  • Supports Forward Error Correction (FEC), cyclic redundancy checks (CRC) and command channel
  • Supports single block, Multi block and extended multi block
  • Provides error injection and error detection with a wide variety of error types. Which includes:
    • Invalid code group insertion
    • Disparity errors
    • CRC errors
    • Sync error insertion
    • Lane skew insertion
    • FEC errors
    • Scrambler error insertion
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
JESD204 Synthesizable Transactor Env

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    SmartDV's JESD204 Synthesizable Transactor env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the JESD204 testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

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