UART Synthesizable Transactor provides an smart way to verify the UART component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's UART Synthesizable Transactor is fully compliant with standard UART 16550 Specification and provides the following features.
- Features
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- Fully compatible with 16550
- Supports transmit and receive commands allow the user to transmit and receive UART data
- Supports additional functionality of IRDA, RS232, RS422, RS485 and GPIO
- Supports full duplex operation
- Supports fully configurable serial interface
- Supports character width from 1 bit to 32 bits
- Supports configurable baud rate
- Supports programmable hardware flow control
- Supports different types of parity insertion:
- Even parity
- Odd parity
- Space parity
- Mark parity
- No parity
- Supports number of stop bit configuration
- Supports 16 General purpose output and input pins
- Configurable receive FIFO depth
- Supports constraints Randomization
- Auto CTS/auto RTS hardware flow control
- GPIO are supported using read and write commands
- Supports IRDA protocol
- Supports error injection capability:
- Parity error
- Framing error
- Supports on-the-fly protocol and data checking
- Ability to transmit strings to help verification of SOC
- Notifies the test bench of significant events such as transactions, warnings, and protocol violations
- UART Synthesizable Transactor comes with complete test suite to verify each and every feature of UART specification
- Status counters for various events in bus
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- UART Synthesizable Env
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SmartDV's UART Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the UART testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
