IEC61162 Verification IP provides an smart way to verify Maritime navigation and Radio Communication equipment and systems when interconnected via an appropriate system. The SmartDV's IEC61162 Verification IP is fully compliant with standard IEC61162 Specification IEC61162-1 and provides the following features.
IEC61162 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
IEC61162 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports IEC61162 Specification.
- Complete IEC61162 talker and listener functionality.
- Supports one-way serial asynchronous data transmission from a single talker to one or more listeners.
- Supports all approved sentence formats and associated fields.
- Configurable Baud rate control.
- Programmable transmission rate and sentence transmission timing/interval.
- Configurable inter-character spacing.
- Programmable character length (20 to a maximum of 79 characters).
- Supports all types of error insertion and detection,
- Checksum field error
- Address field error
- Data field error
- Start of sentence error
- End of sentence error
- Field delimiter error
- Checksum delimiter error
- Status field, Mode indicator field and GPS Quality Indicator field error
- Datum and Positional sentence error
- RMA and digital selective calling sentence error
- Oversize error
- Undersize error
- Supports Variable length fields and all Data field types.
- Flexibility to send completely configured data.
- Rich set of configuration parameters to control the functionality.
- Supports constraints Randomization.
- Status counters for various events on bus.
- Callbacks in talker, listener and monitor for various events.
- IEC61162 Verification IP comes with complete test suite to test every feature of IEC61162 specification.
- Functional coverage for complete IEC61162 features.
- Monitors, detects and notifies the testbench of significant events, protocol and timing violations.
- Benefits
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- Faster testbench development and more complete verification of IEC61162 designs.
- Easy to use command interface simplifies testbench control and configuration of Talker, Listener and monitor.
- Simplifies results analysis.
- Runs in every major simulation environment.
- IEC61162 Verification Env
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SmartDV's IEC61162 Verification env contains following.
- Complete regression suite containing all the IEC61162 testcases.
- Examples showing how to connect various components and usage of Talker, Listener and Monitor.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation contains User's Guide and Release notes.
