The Ethernet 25G,50G Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a Ethernet 25G,50G interface. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. Ethernet 25G,50G Verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.
Ethernet 25G,50G Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Ethernet 25G,50G Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports 25G and 50G Speeds as per the 802.3-2018 specification,
- 25GBase_R
- 25GBase_KR
- 50GBase_KR
- 50GBase_KR2
- Supports FEC
- Supports scrambler
- Supports backplane auto-negotiation
- Supports Link training
- Supports Pause frame generation and detection.
- Supports MDIO slave and master model as per Clause 22 and Clause 45
- Glitch insertion and detection
- PCS to Serdes interface supports all widths
- Supports CDR for serial protocols
- Supports the upper layer protocols
- Full support for IEEE 802.1AZ (Energy Efficient Ethernet)
- Full support for IEEE 1588-2002 and IEEE 1588-2008
- Ethernet Verification IP comes with complete UNH Test suite
- Supports all types of TX and RX errors insertion/detection at each layer.
- Oversize, undersize, inrange, out of range Packet size errors
- Missing SPD/EPD/SFD framing errors
- SFD on wrong lane
- CRC Error
- Lane skew insertion
- Invalid /D/ and /K/ character injection
- Variable preamble and IPG insertion
- Invalid block code insertion
- Sync bit corruption
- FEC error injection
- Scrambler error injection
- Comes with Tx BFM,Rx BFM, and Monitor.
- Monitor supports detection of all protocol violations.
- Built in coverage analysis.
- Status counters for various events in bus
- Benefits
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- Faster testbench development and more complete verification of Ethernet 25G,50G designs
- Easy to use command interface simplifies testbench control and configuration of TX and RX
- Simplifies results analysis
- Runs in every major simulation environment
- Ethernet 25G,50G Verification Env
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SmartDV's Ethernet 25G,50G Verification env contains following.
- Complete regression suite (UNH) containing all the Ethernet 25G,50G testcases.
- Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
