• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IPs
      • MIPI Verification IPs
      • Networking and SOC Verification IPs
      • Automotive And Serial Bus Verification IPs
      • Storage And Video Verification IPs
    • Memory Models
      • DDR SDRAM Memory Models
      • DFI Verification IPs
      • DIMM Memory Models
      • Flash Memory Models
      • Graphics Memory Models
      • High Bandwidth Memory Models
      • Low Power Memory Models
      • Misc Memory Models
      • Non volatile Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • Non volatile Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
      • DFI Synthesizable Transactors
    • Formal Verification IPs (Assertion IP)
      • Networking and SOC Assertion IPs
      • DDR SDRAM Memory Assertion IPs
      • Low Power Memory Assertion IPs
      • Graphics Memory Assertion IPs
      • High Bandwidth Memory Assertion IPs
      • SDRAM Memory Assertion IPs
      • DFI Assertion IPs
      • Serial Assertion IPs
    • Post Silicon Validation IPs
      • MIPI Post Silicon Validation IPs
    • Design IPs
      • DDR Controller Design IPs
      • Ethernet Design IPs
      • Serial Bus Design IPs
      • Audio Video Design IPs
      • MIPI Design IPs
      • Automotive Design IPs
      • Bridge Design IPs
      • DMA Controller Design IPs
      • Flash Controller Design IPs
      • High Speed Design IPs
      • SpeedBridge IPs
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

AMBA ATB Verification IP

AMBA ATB Verification IP

AMBA ATB Verification IP provides a smart way to verify the AMBA ATB component of a SOC or an ASIC. The SmartDV's AMBA ATB Verification IP is fully compliant with standard AMBA ATB Specification. Our AMBA ATB VIP is proved across multiple customers.

AMBA ATB Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

AMBA ATB Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Compliant to ARM AMBA 3 ATB (ATB v1.0) and AMBA 4 ATB (ATB v1.1) Protocol.
  • Support AMBA ATB Master, ATB Slave, ATB Monitor and ATB Checker.
  • Support for multiple masters and slaves.
  • Supports all ARM AMBA ATB data, byte and ID widths.
  • ATB 1.0/ATB 1.1 common support
    • Supports Flow control - valid/ready signaling for trace data.
    • Supports Flush Request Response control - Flush valid/ready signaling with trace data.
    • Supports capturing of valid trace data.
    • Supports master internal buffer storage,configurble of trace sources to store trace locally or not.
    • Supports constrained randomization of protocol attributes.
    • Flexibility to send completely configured data.
    • Programmable ID's for the trace transfers.
    • Programmable Timeout insertion.
    • Ability to inject errors during data transfer.
  • ATB 1.1 support
  • In addition to ATB 1.0 support, ATB 1.1 supports the following features,
    • Supports enable and disable access for clock.
    • Supports Synchronization Request operations.
    • Supports triggering operations.
  • Supports FIFO memory.
  • Rich set of configuration parameters to control ATB functionality.
  • On-the-fly protocol and data checking.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in coverage analysis.
  • Callbacks in master, slave and monitor for various events.
  • Status counters for various events on bus.
  • ATB Verification IP comes with complete testsuite to test every feature of ARM AMBA ATB specification
Benefits
  • Faster testbench development and more complete verification of AMBA ATB designs.
  • Easy to use command interface simplifies testbench control and configuration of master and slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
AMBA ATB Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's AMBA ATB Verification env contains following.

  • Complete regression suite containing all the AMBA ATB testcases.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

About SmartDV
Partners
Careers
Products
Customers
News & Events

Verification IP
Memory Models
SimXL - Emulation Models
Formal Verification IP (Assertion IP)
Post-Silicon Validation IP
Design IP

info@smart-dv.com

Contact Us
Support
Copyright © SmartDV Technologies India Private Limited All rights reserved.