TileLink Assertion IP provides an smart way to verify the TileLink component of a SOC or an ASIC. The SmartDV's TileLink Assertion IP is fully compliant with standard TileLink Specification 1.8.1 and provides the following features.
TileLink Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
TileLink Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Compliant with TileLink specification version 1.8.1.
- Supports TileLink Uncached Lightweight (TL-UL), TileLink uncached Heavy weight (TL-UH) and TileLink Cached (TL-C) conformance levels.
- Supports Cache-coherent shared memory.
- Out-of-order completion support.
- Burst fragmentation support.
- Ability to configure the width of all signals.
- On-the-fly protocol and data checking.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV TileLink VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure TileLink Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- TileLink Assertion Env
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SmartDV's TileLink Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
