AMBA 5 AHB Bus Verification IP provides a smart way to verify the AMBA 5 AHB component of a SOC or an ASIC. The SmartDV's AMBA 5 AHB Bus Verification IP is fully compliant with standard AMBA 5 AHB specification.
AMBA 5 AHB Bus Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA 5 AHB Bus Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with ARM AMBA 5 AHB specification.
- Supports AMBA 5 AHB Master, Slave, Bus, Monitor and Checker.
- Support for multiple Masters and slaves.
- Supports all AMBA 5 AHB data widths and address widths.
- Supports all protocol transfer types, burst transfers and response types.
- Support for all the transfer sizes.
- Supports Extended memory types
- Support for Secure transfers
- Supprot for Endianess
- Supports Stable between clock
- Exclusive and Locked Transfers support
- Multi-Copy Atomicity support
- Multiple slave select support
- Single-copy atomicity size support
- User signaling support
- Supports constrained randomization of protocol attributes.
- Slave supports fine grain control of response per address or per transaction.
- Master supports fine grain control of busy state insertion and Master aborting.
- Supports Early burst termination and locked transfers.
- Continue or cancel of a transfer on error response.
- Support for programmable wait states or delay insertion.
- Ability to inject errors during data transfer.
- Programmable Timeout insertion.
- Flexibility to send completely configured data.
- Supports FIFO memory.
- Rich set of configuration parameters to control AMBA 5 AHB functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in coverage analysis.
- Callbacks in Master, Slave, Bus and Monitor for various events.
- Status counters for various events on bus.
- AMBA 5 AHB Bus Verification IP comes with complete testsuite to test every feature of AMBA 5 AHB specification.
- Benefits
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- Faster testbench development and more complete verification of AMBA 5 AHB designs.
- Easy to use command interface simplifies testbench control and configuration of Master, Slave and Bus.
- Simplifies results analysis.
- Runs in every major simulation environment.
- AMBA 5 AHB Bus Verification Env
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SmartDV's AMBA 5 AHB Bus Verification env contains following.
- Complete regression suite containing all the AMBA 5 AHB testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
