SGPIO (Serial GPIO) Bus Verification IP provides an smart way to verify the SGPIO bus. The SmartDV's SGPIO Verification IP is fully compliant with SFF-8485 Specification Revision 0.7 Specification and provides the following features.
SGPIO Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SGPIO Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7.
- Full SGPIO Initiator and SGPIO Target functionality.
- Supports upto 256 hard disk.
- Supports operating frequency from 33 Hz to 100 KHz.
- Support to control SCLK High and Low time.
- SGPIO initiator includes two blink generators A and B that may be used to control the output patterns.
- SGPIO initiator operates in one of two modes:
- Supports below different types of registers,
- Configuration registers
- Receive registers
- General purpose receive registers
- Transmit registers
- General purpose transmit registers
- Callbacks in initiator, target and monitor for various events.
- Status counters for various events in bus.
- Notifies the testbench of significant events such as transactions, warnings,timing and protocol violations.
- Functional coverage of complete SGPIO SFF-8485 specs.
- SGPIO Verification IP comes with complete testsuite to test every feature of SGPIO specification.
- Benefits
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- Faster testbench development and more complete verification of SGPIO designs.
- Easy to use command interface simplifies testbench control and configuration of Initiator and Target.
- Simplifies results analysis.
- Runs in every major simulation environment.
- SGPIO Verification Env
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SmartDV's SGPIO Verification env contains following.
- Complete regression suite containing all the SGPIO testcases.
- Examples showing how to connect various components, and usage of Initiator, Target and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
