VRAM Memory Model provides an smart way to verify the VRAM component of a SOC or a ASIC. The SmartDV's VRAM memory model is fully compliant with standard VRAM Specification and provides the following features.
VRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
VRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports DRAM : 262144 Words × 4 Bits
- Supports SAM : 512 Words × 4 Bits
- Supports Dual Port Accessibility- Simultaneous and Asynchronous access from the DRAM and SAM Ports
- Supports Bidirectional Data - Transfer function from the DRAM to the Serial-Data register and from Serial Data Register to DRAM
- Supports (8 x 8) x 2 Block write feature for fast area fill
- Supports Write-Per-Bit Feature for selective write to each RAM I/O; Two Write-Per-bit Modes to simplify system design
- Supports Byte-write Control (CASL, CASU) which provides flexibility
- Supports Enhanced Page-Mode Operation for faster access
- Supports mask write mode capability
- Supports Extended data output for faster system cycle time
- Supports CAS-Before-RAS (CBR) and hidden Refresh modes
- Supports 3 variations of refresh (8 ms/512 cycles)
- RAS-only refresh
- CAS-before-RAS refresh
- Hidden refresh
- Supports Up to 50MHz uninterrupted Serial-Data Streams
- Supports 3 State Serial I/O’s allow easy multiplexing of Video-Data streams
- Supports 512 selectable Serial-Register starting locations
- Supports SE Controlled Register status QSF
- Supports split Serial-Data Register for simplified Real-Time register reload
- Supports programmable Split-Register stop point
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster testbench development and more complete verification of VRAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- VRAM Verification Env
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SmartDV's VRAM Verification env contains following.
- Complete regression suite containing all the VRAM testcases.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
