DALI Synthesizable Transactor provides a smart way to verify the DALI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DALI Synthesizable Transactor is fully compliant with standard DALI Specification and provides the following features.
- Features
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- Fully compatible with IEC 62386-101 Edition 2.0 2014-11 and IEC 62386-102 Edition 2.0 2014-11 Specifications
- Supports complete DALI Tx/Rx functionality
- Supports fully configurable serial interface
- Supports programmable clock frequency of operation
- Supports configurable baud rate
- Supports two types of frame formats
- 16-Bit Forward Frame
- 20-Bit Reserved Forward Frame
- 24-Bit Forward Frame
- 32-Bit Reserved Forward Frame
- Backward frame
- Supports different Device addressing method
- Short address
- Group address
- Broadcast unaddress
- Broadcast address
- Special command address
- Reserved address
- Supports direct arc power control (DAPC) command
- Supports manchester encoding/decoding technique
- Supports collision avoidance, collision detection and collision recovery
- Supports all types of error insertion and detection
- Start bit error
- Stop bit errors
- Response Timeout error
- Manchester Encoding errors
- Bi-phase Encoding errors
- Framing errors
- Supports Glitch insertion and detection
- DALI VIP comes with complete testsuite to test every feature of DALI specification
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- DALI Synthesizable Env
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SmartDV's DALI Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the DALI testcases
- Examples showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
