ARINC 825 Synthesizable Transactor provides a smart way to verify the ARINC 825 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's ARINC825 Synthesizable Transactor is fully compliant with standard ARINC 825 Specification and provides the following features.
- Features
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- Supports ARINC REPORT 825 - 2
- Supports transmission data rates from 83.333 Kbps to 1Mbps
- Supports one-to-many communication and also peer-to-peer communication
- Supports all the four frame types
- Data frames
- Remote frames
- Error frames
- Overload frames
- Remote frame support
- Supports automatic transmission after reception of remote transmission request (RTR)
- Supports automatic receive after transmission of an RTR
- Supports all the five types of error insertion and detection
- Bit errors
- Stuff errors
- CRC errors
- Format errors
- Acknowledgement errors
- Tracks TEC/REC error counter and fault states
- Supports bit by bit Arbitrations
- Supports glitch insertion and detection
- Supports re-transmission of corrupted messages
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- ARINC 825 Synthesizable Env
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SmartDV's ARINIC825 Synthesizable env contains following:
- Complete regression suite containing all the LVDS testcases
- Synthesizable transactors
- Examples showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
