AMBA AXI5-Lite Interconnect Verification IP provides an smart way to verify the ARM AMBA AXI5-Lite component of a SOC or a ASIC. The SmartDV's AMBA AXI5-Lite Interconnect Verification IP is fully compliant with standard AMBA AXI5-Lite Specification.
AMBA AXI5-Lite Interconnect Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA AXI5-Lite Interconnect Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with the latest ARM AXI5-Lite Protocol Specification.
- Supports AXI5-Lite Master, Slave, Interconnect, Monitor and Checker.
- Supports all AXI5-Lite data and address widths.
- Supports all protocol transfer types, burst types, burst lengths, burst sizes and response types.
- Supports constrained randomization of protocol attributes.
- Separate address/control, data and response phases. Separate read and write channels.
- Support for burst-based transactions with only start address issued.
- Slave, Interconnect and Master support fine grain control of response per address or per transaction.
- Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
- Ability to inject errors during data transfer.
- Write strobe support to enable sparse data transfer on the write data bus.
- Narrow transfer support.
- Unaligned address access support.
- Protected accesses with normal/privileged,secure/non-secure and data/instruction
- Ability to configure the width of all signals.
- Support for conversion of different protocols and different data width.
- Support for bus inactivity detection and timeout.
- Configurable WID signal enable support.
- Quality of Service signaling.
- Multiple region interfaces.
- User signaling support.
- Supports unmapped region address accesses
- AWCACHE and ARCACHE Attributes.
- Low-power Interface support
- Write strobe support.
- Data bus width of 32-bit or 64-bit.
- AXI5-Lite specific features
- All transactions burst length 1.
- Reordering of responses for requests with different IDs.
- All accesses Device Non-bufferable.
- Atomic access support with normal access.
- Programmable Timeout insertion.
- Supports FIFO memory.
- Rich set of configuration parameters to control AXI5-Lite functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in coverage analysis.
- Callbacks in Master, Slave, Interconnect and Monitor for various events.
- Status counters for various events on bus.
- AXI5-Lite Interconnect Verification IP comes with complete testsuite to test every feature of ARM AMBA AXI5-Lite specification.
- Benefits
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- Faster testbench development and more complete verification of AMBA AXI5-Lite designs.
- Easy to use command interface simplifies testbench control and configuration of Master, Slave and Interconnect.
- Simplifies results analysis.
- Runs in every major simulation environment.
- AMBA AXI5-Lite Interconnect Verification Env
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SmartDV's AMBA AXI5-Lite Interconnect Verification env contains following.
- Complete regression suite containing all the AMBA AXI5-Lite testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
