Avalon Verification IP provides an smart way to verify the Avalon Interface component of a SOC or a ASIC. The SmartDV's Avalon Verification IP is fully compliant with Intel's Avalon Interface Specification. VIP includes an extensive test suite covering all the possible scenarios.
Avalon Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Avalon Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with Intel's Avalon Interface specification.
- Supported interfaces and compnonents:
- Avalon Memory-Mapped (Avalon-MM) Master and Slave interfaces
- Avalon Streaming (Avalon-ST) Source and Sink interfaces
- Avalon Conduit interfaces
- Avalon Tristate Conduit (Avalon-TC) interfaces
- Avalon Interrupt Source and Sink interfaces
- Avalon Clock Source and Sink interfaces
- Avalon Reset Source and Sink interfaces
- Supported monitors:
- Avalon-MM Monitor
- Avalon-ST Monitor
- Avalon-MM Interface support
- Supports all address and data widths.
- Supports all Typical, Pipelined and Burst transfer types.
- Components support fine grain control of response per address or per transaction.
- Avalon-ST Interface support
- Supports all transfer types.
- Avalon Conduit Interface support
- Supports to connect individual or group of non avalon signals.
- Avalon-TC Interface support
- Supports to reduce the number of signals and pin count.
- Avalon Interrupt Interface support
- Supports point to point connection between two systems, one generating an interrupt and another receiving it.
- Supports constrained randomization of protocol attributes.
- Programmable wait states or delay insertion.
- Ability to inject errors during transaction.
- Programmable Timeout insertion.
- Supports FIFO memory.
- Rich set of configuration parameters to control Avalon Interface functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in coverage analysis.
- Callbacks in components and monitors for various events.
- Status counters for various events on interface.
- Avalon Verification IP comes with complete testsuite to test every feature of Intel's Avalon Interface specification.
- Benefits
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- Faster testbench development and more complete verification of Avalon Interface designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Avalon Verification Env
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SmartDV's Avalon Verification env contains following.
- Complete regression suite containing all the Avalon testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
