LPC Host interface is full-featured, easy-to-use, synthesizable design, compatible with Standard LPC specification. Through its LPC compatibility, it provides a simple interface to a wide range of low-cost devices. LPC Host IIP is proven in FPGA environment.The host interface of the LPC Host can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite,AMBA AXI,AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink,Wishbone or Custom protocol.
LPC Host IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with version 1.1 LPC Specifications.
- Full LPC Host functionality.
- Supports the following operations:
- Memory read and write
- I/O read and write
- DMA read and write
- Bus Master memory read and write
- Bus Master I/O read and write
- Firmware memory read and write
- Supports all transfer sizes
- Supports 128 Bytes for Firmware read
- Supports variable number of wait-states
- Supports Sync timeout detection and abort transfer
- Supports Sync field based error detection and reporting
- Supports wake-up and other power state transitions
- Supports both typical timing and extended timing for LFRAME#
- Host is capable of generating all types of LPC transactions
- Support upto 32 SERRIRQ IRQ/Data frames
- Supports Abort Mechanism as per specification
- Supports soft reset
- Supports Reset policy
- Supports LPME#, LPCPD#, CLKRUN# Power management signals
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IIP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's LPC Host IP contains following.
- The LPC Host interface is available in Source and netlist products.
- The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and linux driver package
- Documentation contains User's Guide and Release notes.
