PMBUS Slave interface provides full support for the two-wire PMBUS Slave synchronous serial interface, compatible with version 1.3.1 Part II of PMBus Bus Specification. Through its PMBUS Slave compatibility, it provides a simple interface to a wide range of low-cost devices. PMBUS Slave IIP is proven in FPGA environment. The host interface of the PMBUS Slave can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
PMBUS Slave IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with version 1.3.1 Part II of PMBus Bus Specification
- Full PMBus Slave Functionality
- Supports the following PMBus commands as per Specification
- Send byte command
- Write byte command
- Write word command
- Read byte command
- Read word command
- Block write command
- Block read command
- Block write and read process call command
- Read 32 protocol
- Group command protocol
- Extended command protocol
- Supports Zone write and Zone read operation
- Supports Slave arbitration
- Supports General call address
- Supports PMBus device fault management
- Supports Packet Error checking(PEC)
- Supports clock stretching
- Supports alert generation
- Supports timeout detection and generation
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's PMBUS Slave IP contains following
- The PMBUS Slave interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
- ISO26262 Safety Manual (SAM) Document
- ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document
