EtherCAT Slave core is compliant with EtherCAT Standard Specification ETG.1000 S(R) V1.0.4. Through its EtherCAT compatibility, it provides a simple interface to a wide range of low-cost devices. EtherCAT Slave IIP is proven in FPGA environment. The host interface of the EtherCAT can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
Ethercat Slave IIP is supported natively in Verilog and VHDL
- Features
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- Supports ETG.1000 S(R) V1.0.4 specification.
- 8 SYNC Manager
- 8 FMMU's
- 8kB Process Data RAM
- 64 Bit Distributed Clocks
- Can connect with SPI/I2C/UART interfaces based on application
- MAC is Compliant with IEEE Standard 802.3.2018 specification
- Supports EtherCAT frame inside an Ethernet frame
- Supports all types of EtherCAT data frames
- Supports the standard TCP-IP and UDP-IP protocols
- Supports Full duplex transmission
- Supports Sync Manager and Mailbox
- Supports Field Bus Memory Management Unit
- Supports Error Detection using Ethernet’s Frame Check Sequence
- Supports MII and RMII Interfaces for Ethernet PHY
- Supports conformance tests as per ETG.7000.2 V1.0.6 specification
- Provides detailed statistics as per the specification
- Supports MDIO (Clause 22 and Clause 45) Interface
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller devices
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's EtherCAT Slave IP contains following
- The EtherCAT interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
