CXP Host core is compliant with standard CXP 1.1/1.1.1/2.0 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices.CXP Host IIP is proven in FPGA environment. The host interface of the CXP can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
CXP HOST IIP is supported natively in Verilog and VHDL
- Features
-
- Compliant with CXP Specification 1.1/1.1.1/2.0.
- Full CXP Host functionality.
- Supports upto 4 connections.
- Supports following Channels,
- Stream Channel
- I/O Channel
- Control Channel
- Supports 8,10,12,14,16 bit depth.
- Supports following bit rates for high speed down connection.
- 1.25 Gbps
- 2.50 Gbps
- 3.125 Gbps
- 5.00 Gbps
- 6.25 Gbps
- 10 Gbps
- 12.5 Gbps
- Supports following bit rates for low speed up connection.
- Supports 8B/10B encoding and 10B/8B Decoding.
- Supports unpacking of all the video formats supported by the CXP v2.0 specification.
- Supports the following color formats.
- Raw
- Mono
- Planar_1 to Planar_15
- BayerGR
- BayerRG
- BayerGB
- BayerBG
- RGB
- RGBA
- YUV_411, YUV_422, YUV_444
- YCbCr_601_411,YCbCr_601_422, YCbCr_601_444
- YCbCr_709_411, YCbCr_709_422, YCbCr_709_444
- Supports packet demultiplexing for different streams.
- Supports connection test facilities to test the quality of the connection.
- Supports Unified Time Stamping as per CXP version 2.0 specification.
- Supports backward compatibility for version 1.1.1 specification.
- High speed up connection with maximum bit rate of 6.25 Gbps
- Low speed up connection with 20.83 Mbps bit rate
- This core achieves ASIL B and can be made to achieve ASIL D as per
- ISO26262
- Benefits
-
- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
-
SmartDV's CXP Host IP contains following
- The CXP Host interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
- ISO26262 Safety Manual (SAM) Document
- ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA)
- Document
