• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IPs
      • MIPI Verification IPs
      • Networking and SOC Verification IPs
      • Automotive And Serial Bus Verification IPs
      • Storage And Video Verification IPs
    • Memory Models
      • DDR SDRAM Memory Models
      • DFI Verification IPs
      • DIMM Memory Models
      • Flash Memory Models
      • Graphics Memory Models
      • High Bandwidth Memory Models
      • Low Power Memory Models
      • Misc Memory Models
      • Non volatile Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • Non volatile Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
      • DFI Synthesizable Transactors
    • Formal Verification IPs (Assertion IP)
      • Networking and SOC Assertion IPs
      • DDR SDRAM Memory Assertion IPs
      • Low Power Memory Assertion IPs
      • Graphics Memory Assertion IPs
      • High Bandwidth Memory Assertion IPs
      • SDRAM Memory Assertion IPs
      • DFI Assertion IPs
      • Serial Assertion IPs
    • Post Silicon Validation IPs
      • MIPI Post Silicon Validation IPs
    • Design IPs
      • DDR Controller Design IPs
      • Ethernet Design IPs
      • Serial Bus Design IPs
      • Audio Video Design IPs
      • MIPI Design IPs
      • Automotive Design IPs
      • Bridge Design IPs
      • DMA Controller Design IPs
      • Flash Controller Design IPs
      • High Speed Design IPs
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

SPI (Serial Peripheral Interface) Verification IP

SPI (Serial Peripheral Interface) Verification IP

SPI (Serial Peripheral Interface) is the serial synchronous communication protocol developed by SPI Block Guide V04.01. SPI VIP can be used to verify Master or Slave device following the SPI basic protocol as defined in Motorola's M68HC11 user manual rev 5.0. It can work with Verilog HDL environment and works with all Verilog simulators that are support SystemVerilog.

SPI (Serial Peripheral Interface) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SPI (Serial Peripheral Interface) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Follows SPI basic specification as defined in SPI Block Guide V04.01
  • Supports SQI interface specification and common flash device models
  • Supports data width from 4 bits to 64 bits.
  • Supports Master and Slave Mode
  • Supports 3-wire, 4-wire SPI interface
  • Supports bus width 1 bit and 4 bit
  • Slave device supported for SPI 3 wire are
    • BOSCH SMB380
    • RICOH R2033K
  • Supports baud rate selection
  • Supports internal clock division check.
  • Supports clock polarity (CPOL) selections.
  • Supports clock phase (CPHA) selection.
  • Supports single and burst transfer mode.
  • Supports on the fly generation of data.
  • Supports daisy-chaining connection.
  • Supports Glitch insertion and detection
  • Detects and reports the Mode Fault error
  • Supports customized single/dual/quad modes for Command, Address and Data phase.
  • Supports configurable dummy cycles.
  • Supports configurable memory density.
  • Supports backdoor access for memory and registers.
  • Built in functional coverage analysis.
  • Supports Callbacks in master, slave and monitor for modifying, and sampling data/cmd on SPI bus.
  • SPI Slave can be configured as standard device or can use FIFO for data passing.
  • In standard model mode, Mater/Slave support different types of devices. Like FLASH, EEPROM, FRAM,RTC,SQI,MOTOROLA Mode,NS mode and TI mode(PRECEDE and cOINCIDE), EMPSPI, MACRONIX, DBI TYPE C, Serial flash and MAXIM.
  • Supports single,dual and quad mode bus width operation
  • Supports spansion DDR model
  • Master contains rich set of commands for both standard device and FIFO model mode.
  • Notifies the test bench of significant events such as transactions, warnings, and protocol violations. This can be written to separate log files.
  • SPI Verification IP comes with complete test suite to test every feature of SPI specification.
Benefits
  • Faster testbench development and more complete verification of SPI designs.
  • Easy to use command interface simplifies testbench control and configuration of slave and master.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
SPI Verification Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's SPI Verification env contains following.

  • Complete regression suite containing all the SPI testcases.
  • Examples showing how to connect various components, and usage of Master, Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

About SmartDV
Partners
Careers
Products
Customers
News & Events

Verification IP
Memory Models
SimXL - Emulation Models
Formal Verification IP (Assertion IP)
Post-Silicon Validation IP
Design IP

info@smart-dv.com

Contact Us
Support

Copyright © SmartDV Technologies India Private Limited All rights reserved.