SBSRAM Memory Model provides an smart way to verify the SBSRAM component of a SOC or a ASIC. The SmartDV's SBSRAM memory model is fully compliant with standard SBSRAM Specification and provides the following features. Better than Denali Memory Models.
SBSRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
SBSRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports SBSRAM memory devices from all leading vendors.
- Supports 100% of SBSRAM protocol standard specifications.
- Supports all the SBSRAM commands as per the specs.
- Supports device density up to 288MB.
- Supports single/dual cycle deselect selectable.
- Supports IEEE 1149.1 JTAG-compatible boundary scan.
- Supports Internal self-timed write cycle. Supports byte write and global write operation.
- Supports automatic power down mode. Supports following burst mode operation.
- Linear burst mode
- Interleave burst mode
- Quickly validates the implementation of the SBSRAM standard specifications.
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- All timing violations.
- Supports callbacks for user to get command data on bus.
- Protocol checker fully compliant with SBSRAM Specifications.
- Constantly monitors SBSRAM behavior during simulation.
- Bus-accurate timing for min, max and typical values.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster testbench development and more complete verification of SBSRAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- SBSRAM Verification Env
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SmartDV's SBSRAM Verification env contains following.
- Complete regression suite containing all the SBSRAM testcases.
- Complete UVM/OVM sequence library for SBSRAM controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
