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I2S Synthesizable Transactor

I2S Synthesizable Transactor

I2S Synthesizable Transactor provides a smart way to verify the I2S bi-directional two-wire bus component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's I2S Synthesizable Transactor is fully compliant with Philip's I2S-Bus Specification June 5, 1996 and provides the following features.

Features
  • Supports Philips I2S Bus Specification June 5, 1996
  • Full I2S Transmitter, Receiver and Controller functionality
  • Supports up to 32 channels in transmit path
  • Supports up to 32 channels in receive path
  • Supports programmable word length 8,12,16,20,24,32
  • Supports programmable padding
  • Supports programmable bit reversal
  • Supports left and right justified
  • Both transmitter and receiver can either work with SCK as input or can drive SCK
  • Supports programmable data rate on transmit path
  • Can operate as master or slave in several configurations
    • Master or slave mode as transmitter
    • Master or slave mode as receiver
    • Master mode as controller (does not transmit or receive data)
  • I2S SimXL comes with complete test suite to test every feature of I2S specification
  • Ability to detect and insert various types of error
  • The model has a rich set of configuration parameters to control I2S functionality
  • Supports fully synthesizable
  • Supports static synchronous design
  • Supports positive edge clocking and no internal tri-states
  • Supports simple interface allows easy connection to microprocessor/microcontroller devices
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
I2S Synthesizable Transactor Env

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    SmartDV's I2S Synthesizable env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the I2S testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

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