MIPI RFFE SPI Slave interface provides full support for the two-wire MIPI RFFE synchronous serial interface with SPI overlay, compatible with RFFE 2.1 and SPI Block Guide V04.01 specification. Through its RFFE compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI RFFE SPI Slave IIP is proven in multiple ASIC.The host interface of the MIPI RFFE/SPI can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom protocol.
MIPI RFFE SPI Slave IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with 3.0 MIPI RFFE Specification and SPI Block Guide V04.01 Specification
- Full MIPI RFFE Slave functionality.
- Supports following frames
- Command Frame
- Data/Address Frame
- No Response Frame
- Supports extended register read/writes
- Supports interrupt summary and identification command sequence
- Support Trigger and Extended trigger modes
- Support Masked write command sequence
- Supports Timed Trigger
- Supports Mappable Triggers
- Support Synchronous read
- Support Normal and Secondary operation mode
- Support USID Programming Procedure 1,2 and 3
- Support Group slave ID
- Supports device enumeration
- Supports Half-Speed Data Response (HSDR) Accesses
- Supports Full Command Sequence at Half-Speed SCLK
- Supports Delayed Read-back
- Supports Reserved Register Allocations in Basic Address Space (0x1C – 0x1F)
- Supports Reserved Register Allocations in Extended Address Space (0x20 – 0x3F)
- Supports Write Slave State via PWR_MODE bits
- Supports Read Slave State via PWR_MODE bits
- Supports Read PRODUCT_ID, MANUFACTURER_ID and USID from reserved registers.
- Support Interrupt capable slave
- Supports Extended Frequency Range up to 52 MHz
- Supports the following Error detections
- Undefined command frame
- Command frame with parity error
- Command frame length error
- Address frame with parity error
- Data frame with parity error
- Read of unused register
- Write of an unused register
- Read using the broadcast ID or a GSID
- Full SPI Slave functionality
- Supports following frames for SPI
- Sleep Frame
- Wakeup Frame
- Write Frame
- Read Frame
- Supports 8 bit and 16 bit address for SPI
- Support single and burst transfer mode for SPI
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Optionally this core can be built to have SPI or I2C interface for application where slave can have multiple interfaces like RFFE or SPI or I2C Interface.
- This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's MIPI RFFE SPI Slave IP contains following.
- The MIPI SPI RFFE Slave interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
- ISO26262 Safety Manual (SAM) Document
- ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA)Document
