TileLink Verification IP provides an smart way to verify the TileLink component of a SOC or a ASIC. The SmartDV's TileLink Verification IP is fully compliant with TileLink Specification Version 1.8.1.
TileLink Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
TileLink Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with TileLink specification Version 1.8.1.
- Supports TileLink Master, TileLink Slave, TileLink Interconnect, TileLink Monitor and TileLink Checker.
- Supports TileLink Uncached Lightweight (TL-UL),TileLink Uncached Heavy weight (TL-UH) and TileLink Cached (TL-C) conformance levels.
- Supports Cache-coherent shared memory.
- Out-of-order completion support.
- Burst fragmentation support.
- Supports all data bus and address field widths.
- Supports constrained randomization of protocol attributes.
- Slave, Interconnect and Master support fine grain control of response per address or per transaction.
- Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
- Ability to inject errors during data transfer.
- Ability to configure the width of all signals.
- Programmable Timeout insertion.
- Supports FIFO memory.
- Rich set of configuration parameters to control TileLink functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in coverage analysis.
- Callbacks in Master, Slave, Interconnect and Monitor for various events.
- Status counters for various events on bus.
- TileLink Verification IP comes with complete testsuite to test every feature of TileLink specification.
- Benefits
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- Faster testbench development and more complete verification of TileLink designs.
- Easy to use command interface simplifies testbench control and configuration of master and slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
- TileLink Verification Env
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SmartDV's TileLink Verification env contains following.
- Complete regression suite containing all the TileLink testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation also contains User's Guide and Release notes.
