UART Assertion IP provides an efficient and smart way to verify the UART designs quickly without a testbench. The SmartDV's UART Assertion IP is fully compliant with standard UART Specification and provides the following features.
UART Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
UART Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Fully compatible with 16550.
- Transmit and receive commands allow the user to transmit and receive UART data.
- Support additional functionality of IRDA, RS232, RS422, RS485 and GPIO.
- Configurable Baud rate control.
- Full duplex operation.
- Fully configurable serial interface.
- Supports character width from 1 bit to 32 bits.
- Supports number of stop bit configuration.
- Supports different types of parity insertion
- Even parity
- Odd parity
- Mark parity
- Space parity
- No parity
- GPIO are supported using read and write commands.
- Supports IRDA protocol.
- Ability to transmit strings to help verification of SOC.
- Supports 16 General purpose output and input pins.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Tx mode, Rx mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV UART VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure UART Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- UART Assertion Env
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SmartDV's UART Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
