GDDR6 DFI Verification IP provides an smart way to verify the GDDR6 DFI component of a SOC or a ASIC. The SmartDV's GDDR6 DFI Verification IP is fully compliant with standard DFI Specification and provides the following features.
GDDR6 DFI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
GDDR6 DFI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with DFI version 4.0 or 5.0 Specifications.
- Supports GDDR6 devices compliant with JEDEC GDDR6 SGRAM Standard JESD250A and JESD250B.
- Supports GDDR6 x16 or x8 clamshell modes.
- Can be configured as a single controller driving two x16 GDDR6 channels simultaneously (x32 total) or two controllers each driving one x16 GDDR6 channel.
- Supports GDDR6 operation at up to 18Gbps.
- Supports GDDR6 error detection code (EDC).
- Supports controller retries read and write transactions after EDC error detected.
- Supports GDDR6 data bus inversion (DBI) and CA bus inversion (CABI).
- Supports Per-bank and All-bank refresh.
- Supports Write Single Mask (WSM) and Write Double Mask (WDM).
- Supports GDDR6 low power modes (self-refresh and power-down).
- Support for GDDR6 device densities from 8 to 32Gb.
- Supports automatic generation and user-controlled initialization sequences.
- Supports read and write commands with or without auto-precharge.
- Supports DRAM Clock disabling feature.
- Supports frequency change operation.
- Supports Low power control features.
- Supports Error signaling.
- Supports CA Training.
- Supports WCK-DQ Training.
- Supports WCK2CK Leveling.
- Supports RDQS Toggle mode.
- Supports all types of timing and protocol violations detection for timing parameters.
- Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI 4.0 or 5.0 Specifications.
- Bus-accurate timing for min, max and typical values.
- Notifies the test bench of significant events such as transactions, warnings.
- Built in functional coverage analysis.
- Supports callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster test bench development and more complete verification of GDDR6 DFI designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- GDDR6 DFI Verification Env
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SmartDV's GDDR6 DFI Verification env contains following.
- Complete regression suite containing all the GDDR6 DFI testcases.
- Complete UVM/OVM sequence library for GDDR6 DFI controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation also contains User's Guide and Release notes.
