TileLink Synthesizable Transactor provides a smart way to verify the TileLink component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's TileLink Synthesizable Transactor is fully compliant with standard TileLink Specification 1.8.1 and provides the following features
- Features
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- Compliant with TileLink specification Version 1.8.1.
- Supports TileLink Master, TileLink Slave and TileLink Interconnect.
- Supports TileLink Uncached Lightweight (TL-UL),TileLink Uncached Heavy weight (TL-UH) and TileLink Cached (TL-C) conformance levels.
- Supports Cache-coherent shared memory.
- Out-of-order completion support.
- Burst fragmentation support.
- Supports constrained randomization of protocol attributes.
- Slave, Interconnect and Master support fine grain control of response per address or per transaction.
- Programmable wait states or delay insertion on different channels. Interconnect has the ability to replicate Master/Slave inserted delays.
- Ability to inject errors during data transfer.
- Ability to configure the width of all signals.
- Programmable Timeout insertion.
- Rich set of configuration parameters to control TileLink functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, timings and protocol violations.
- Callbacks in Master, Slave and Interconnect for various events.
- Status counters for various events on bus.
- TileLink Synthesizable Transactor comes with complete testsuite to test every feature of TileLink specification.
- Benefits
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- Compatible with testbench writing using SmartDV VIP's.
- All UVM sequences/testcases written with VIP can be reused.
- Runs in every major emulators environment.
- Runs in custom FPGA platforms.
- TileLink Synthesizable Transactor Env
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SmartDV's TileLink Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the TileLink testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
