The 100G Ethernet Verification IP is compliant with IEEE 802.3ba specifications and verifies MAC-to-PHY layer interfaces of designs with a 100G Ethernet interface CGMII. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. Ethernet Verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.
CGMII 100G Ethernet Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
CGMII 100G Ethernet Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Follows CGMII specification as defined in IEEE 802.3ba
- Supports all types of CGMII TX and RX errors insertion/detection
- Oversize, undersize, inrange, out of range Packet size errors
- Missing SPD/EPD/SFD framing errors
- CRC Error
- Variable preamble and IPG insertion
- Invalid /D/ and /K/ character injection
- Comes with CGMII Tx BFM, CGMII Rx BFM, and CGMII Monitor
- Monitor supports detection of all protocol violations
- Supports Pause frame generation and detection
- Built in coverage analysis
- Callbacks in master and slave for various events
- Status counters for various events in bus
- Benefits
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- Faster testbench development and more complete verification of CGMII designs
- Easy to use command interface simplifies testbench control and configuration of CGMII TX and RX
- Simplifies results analysis
- Runs in every major simulation environment
- CGMII 100G Ethernet Verification Env
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SmartDV's CGMII Verification env contains following.
- Complete regression suite containing all the testcases.
- Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
