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SPDIF Synthesizable Transactor

SPDIF Synthesizable Transactor

SPDIF Synthesizable Transactor provides an smart way to verify the SPDIF component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's SPDIF Synthesizable Transactor is fully compliant with IEC 60958 Specification and provides the following features.

Features
  • Supports full SPDIF functionality as per specs IEC 60958 and IEC 61937
  • Supports SMPTE 337M standards for non Linear PCM Audio
  • Supports AES/EBU, AES3 standards for Linear PCM Audio
  • Supports following sampling/driving rates,
    • 32 kHz
    • 22.05 kHz
    • 24 kHz
    • 768 kHz
    • 384 kHz
    • 352.8 kHz
    • 1536 kHz
    • 44.1 kHz
    • 48 kHz
    • 88.2 kHz
    • 96kHz
    • 176.4 kHz
    • 192 kHz
  • Supports 32 audio channels.
  • Configurable Baud rate control.
  • Supports the Biphase-mark code.
  • Supports start bit correction.
  • Supports clock recovery circuit.
  • Supports injection of various errors
    • Preamble error
    • Channel status error
    • Parity Error
    • Various field errors
  • SPDIF Synthesizable Transactor comes with complete testsuite to verify each and every feature of SPDIF specification.
  • On-the-fly protocol and data checking.
  • Supports programmable FIFO depth.
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
SPDIF Synthesizable Transactor Env

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    SmartDV's SPDIF Synthesizable env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the SPDIF testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

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